The Ethernet 40G, 100G Verification IP validates the MAC-to-PHY and PHY-to-MAC layer interfaces of designs having an Ethernet 40G, 100G interface in accordance with IEEE 802.3ba and IEEE 802.3bj requirements. It can operate in environments that use SystemVerilog, Vera, SystemC, E, and Verilog HDL. Experts in Ethernet who have created ethernet products for businesses like Intel, Cortina-Systems, Emulex, and Cisco have created Ethernet 40G, 100G verified IP. We are aware of the steps necessary to validate an Ethernet product. Ethernet 40G,100G Verification IP comes with an optional Smart Visual Protocol Debugger, a GUI-based debugger to speed up debugging. Ethernet 40G,100G Verification IP is natively supported in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, System C, VERA, Specman E and nonstandard verification environments.
Supports 1G
Supports GMII
Supports TBI (i.e Output of 8b/10b PCS)
Supports SGMII(10M/100M/1000M) as per specification 1.8
Supports QSGMII as per specification 1.2
Supports USGMII as per specification 3.0 and 3.1(5G and 10G)
Supports RGMII(10M/100M/1000M),RTBI as per specification 2.0, Supports 1000Base-KX
Supports 1GBASE-SX and 1GBASE-LX
Supports clause 73 backplane auto-negotiation
for 1000Base-KX, Supports clause 37 autonegotiation
Supports SGMII, QSGMII auto-negotiation
Supports USGMII auto-negotiation and packets
Supports full duplex and half duplex ofnoperation
Supports 40G as per 802.3ba
Supports XLGMII
Supports 40GBase-KR4/40GBase-CR4/40GBase-SR4/40GBase-LR4, and XLAUI
Supports FEC, Supports scrambler
Supports backplane auto-negotiation
Supports Link training
Supports 100G as per 802.3ba and 802.3bj
Supports 100GBase-KR10/100GBase-CR10/100GBase-SR10
Supports 100GBase-ER4/100GBase-LR4
Supports 100GBase-KR4/KR/KR/R
Supports 100GBASE-KP4 with PMA enable.
Supports CAUI_4 and CAUI10
Supports RS_FEC(clause 91) and Fire-code FEC
Supports MDIO slave and master model as per Clause 22 and Clause 45
Glitch insertion and detection
Supports CDR for serial protocols
Supports the upper layer protocols
Full support for IEEE 802.1AZ support for IEEE 1588-2002 and IEEE 1588-2008
Supports all types of TX and RX errors insertion/detection at each layer.
Missing SPD/EPD/SFD framing errors
SFD on wrong lane
CRC Error, Lane skew insertion
Invalid /D/ and /K/ character injection
Variable preamble and IPG insertion Comes with Tx BFM,Rx BFM, and Monitor
Deliverables
Complete regression suite containing all the MIPI DSI-2 testcases.
Examples showing how to connect various components, and usage of Tx,Rx and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.
