Description
A popular HDLC transmission protocol is supported in a number of different ways by the HDLC IP Core. It controls address appending and detection during the bit stuffing operation. As if that weren't enough, this Core also offers CRC16 and CRC32 calculation. Thanks to the availability of separate receiver and transmitter FIFO buffers, maskable interrupt, and DMA interface request, the system performance is increased and CPU overload is decreased. Because the HDLC is a fully scalable IP Core, it is the ideal choice for high-end and deeply embedded projects. Small 8-bit SRAM-like interfaces, 32-bit complete AXI4 slave interfaces with burst support, AXI4Lite interfaces, and AHB and APB slave interfaces can also be given, depending on the demands of your project. The Frame Status Buffer is optional.
Features
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Two separate receiver and transmitter interfaces.
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Two separate, configurable FIFO buffers for receiver and transmitter
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Bit stuffing and unstuffing
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Address recognition for receiver and address insertion for transmitter
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Two or one byte address field
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CRC-16 and CRC-32 computation and checking
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Collision detection
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Byte alignment error detection
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Programmable number of bits for idle detection
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NRZI coding support
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Shared flags, shared zeroes support
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Pad fill with flags option
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Transmitter clock generation
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8-bit, 16-bit, 32-bit CPU interface
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Interrupt output for handling control flags and FIFOs’ filling
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Configurable core parameters
Deliverables
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Source code:
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VHDL Source Code or/and
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VERILOG Source Code or/and
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Encrypted, or plain text EDIF
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VHDL & VERILOG test bench environment
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Active-HDL automatic simulation macros
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ModelSim automatic simulation macros
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Tests with reference responses
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Technical documentation
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Installation notes
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HDL core specification
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Datasheet
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Synthesis scripts
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Example application
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Technical support
Applications
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CPU based applications with serial interface based on HDLC/SDLC protocol
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Telecommunication
