Description
The MIPI Camera Serial Interface (CSI-2) is an interface between a camera and an image-processing engine. MIPI CSI Transmitter is used in mobile and high–speed serial applications where a camera can send the video data using it over MIPI lines to the MIPI CSI Receiver for decoding the data and use it for subsequent processing. MIPI CSI Transmitter adheres to MIPI CSI Specification. The MIPI CSI Transmitter along with MIPI DPHY provides a complete solution for encoding MIPI data.
The MIPI CSI-2 Receiver, along with MIPI CSI-2 transmitter and MIPI DPHY/CPHY, provides a complete solution for MIPI CSI-2 communication.
Features
-
Compliant with MIPI CSI Standard v2.x and MIPI D-PHY Standard v1.x, MIPI D-PHY Standard V2.x and MIPI C-PHY V1.x
-
Up to 3 Gsps per trio using C-PHY. 17Gbps in 3 Trios
-
Up to 2.5 Gbps per data lane of D-PHY (V2.0). 10Gbps in 4 Lanes
-
Programmable 1, 2, 3 (C-PHY) or 4 (D-PHY) Data Lane Configuration
-
Configurable for up to 4 virtual channels
-
Functional in continuous and non-continuous clock
-
modes
-
Color Modes: 16, 18, 24 and 36 bpp
-
Color Formats: YUV420 8, 10bits and without CSPS and Legacy, YUV422 8, 10bits, RGB-888, 565, 666, 555 and 444. RAW6, 7, 8, 10, 12 and 14
-
Registering of configuration through CCI interface
-
Host Interface in Pixel or AXI interface formats
Deliverables
-
Configurable RTL Code
-
HDL-based test bench and behavioral models
-
Test cases
-
Protocol checkers, bus watchers, and performance monitors
-
Configurable synthesis shell
-
Documentation
-
Design guide
-
Verification guide
-
Synthesis guide
Benefits
-
Data lane count
-
Color modes
-
Pixel interface width
-
Application interface –Pixel or AXI
-
Command FIFO depth
-
Highly modular and configurable design
-
Layered architecture
-
Active low async reset
-
Clearly demarcated clock domains
-
Extensive clock gating support
Applications
-
Mobile
-
IOT
-
Automotive
-
Wearables
