The D-PHY specification, version 1.2, is perfectly complied with by the MIPI D-PHY Analog RX IP Core. Supported protocols include the Display Serial Interface (DSI) and MIPI Camera Serial Interface (CSI-2). This RX PHY consists of one clock lane and four data lanes. The D-PHY is made up of an analogue front end for creating and receiving electrical level signals and a digital back end for managing I/O operations. internally terminated resistor that is automatically calibrated.
Compliant to MIPI Alliance Standard for
D-PHY specification Version 1.2
Supports standard PPI interface compliant to MIPI Specification
Supports synchronous transfer at high-speed mode with a bit rate of 80-2500 Mb/s
Supports asynchronous transfer at low power mode with a bit rate of 10 Mb/s
Supports ultra-low power mode, high-speed mode and escape mode
Supports one clock lane and up to four data lanes
Data lanes support transfer of data in high-speed mode
Supports error detection mechanism for sequence errors and contentions
Supports contention detection
Configurable skew option for each Clock and Data lanes
Silicon Proven in SMIC 55LP
Deliverables
GDSII & layer map
Place-Route views (.LEF)
Liberty library (.lib)
Verilog behaviour model
Netlist & SDF timing
Layout guidelines, application notes
LVS/DRC verification reports
