Description and Features
Octal SPI master is a fully functional, simple-to-use, synthesizable design that complies with the Octal SPI REV.1.0 protocol set out by Macronix (MX66LM1G45G). It gives a wide range of inexpensive devices a straightforward interface thanks to its octal SPI master compatibility. OCTAL SPI Master IP is proven in FPGA environment. The host interface of the OCTAL SPI master can be AMBA APB, AMBA AHB, AMBA AHB-Lite, AMBA AXI, AMBA AXI-Lite, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
Features
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Full Octal SPI Master Functionality
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Fast frequency support (Up to 133MHz)
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Compliant to the SPI de-facto standard
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Single, dual, quad, and octal serial data lines
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Software programmable transmission formats (CPOL and CPHA)
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Up to 16 slaves supported under master control
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Configurable SPI transfers
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Fast sampling clock input for the SPI transfers
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SPI Block Specs compliant
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FIFOs used for transferring data (configurable depth)
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Full duplex operation
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LSB or MSB mode
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8-bit, 16-bit, 24-bit, and 32-bit synchronous serial transmission
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Software programmable SCLK rate
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Supports DMA/HCI (Host controller Interface) mode of operation.
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Interrupt control
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Fully synthesizable
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Static synchronous design
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Positive edge clocking and no internal tri-states
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Scan test ready
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Simple interface allows easy connection to microprocessor/microcontroller devices.
Deliverables
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The Octal SPI master interface is available in Source and netlist products.
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The Source product is delivered in plain text Verilog. If needed VHDL, SystemC code can also be provided.
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Easy to use Verilog Test Environment with Verilog Testcases
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Lint, CDC, Synthesis, Simulation Scripts with waiver files
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IP-XACT RDL generated address map
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Firmware code and Linux driver package
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Documentation contains User's Guide and Release notes.
