Ethernet MAC Controller IP

Description

The Giga MAC IP is an embedded Fast Ethernet controller module. It is compliant with IEEE 802.3 specification for 10/100Mbps Ethernet and the IEEE802.3ab specification for 1000Mbps Ethernet MAC. The integrated checksum offload engines enable the automatic generation TCP Level checksum for received and transmitted Ethernet Frame, support TCP segmentation and UDP fragment to offload the task from the CPU for Linux OS applications. By using a 32-bit CPU local bus and memory local bus, it provides a standard interface to the host CPU. The Ethernet Controller interfaces to the IEEE Std 802.3u MII interface as well as RMII interface, to the IEEE Std 802.3ab RGMII interface, and also support IEEE 802.3x full-duplex flow control.

Features

• Supports CPU local bus interface for controlling Ethernet MAC internal registers.
• Supports 32-bit memory local bus interface
• Comply with IEEE 802.3u MII interface.
• Support Reduced MII interface
• Support Reduced GMII interface
• Full Duplex/Half Duplex capability for 10M/100M MAC
• 1000M MAC only supports Full-duplex.
• Support IEEE 802.3x full Duplex Flow Control
• Support IEEE 802.1Q VLAN tagging (Tagged MAC frame)
• Supports wake-on-LAN function and remote wake-up (Magic packet and Link Status Change).
• Integrated two large integrated transmit (2KB) and receive (16KB) FIFO Devices.
• Supports a 28-bit general purpose timer with the MAC clock as the clock source, to generate timer interrupt.

Deliverables

• RTL design in Verilog
• Synthesis scripts
• Technical documents
• Sample device drivers