USB3.1Type-C PHY IP is a high performance high speed SERDES IP designed for chips that perform high bandwidth data communication while operating at low power consumption. USB 3.1Type-C PHY IP is a dedicate design for USB3.1 type-C application. USB 3.1 Type C PHY IP is a pure analog IP that perform serialization and deserialization only, a dedicate PCS can be provided together with PHY to accomplish functions of different application, including elastic buffer, scramble/de-scramble, data encoding/decoding, PRBS generation/checking, registers control and testing. PCS is provided as either hard or soft macro based on customer’s request, the specification of PCS will also be provided separately PHY functionality is verified in NC-Verilog simulation software using test bench written in Verilog HDL.
Deliverables
Physical Layout Data with Layer Specifications
LEF Representation of Placement and Routing Topology
Timing and Power Characteristics Library in Liberty Format
Functional Behavior Description in Verilog HDL
Circuit Description and Timing Constraints in Standard Delay Format
Recommendations and Insights for Layout Design
Reports on Layout Versus Schematic and Design Rule Compliance
