Description
The DVB-S2-LDPC-BCH block is a powerful FEC (Forward Error Correction) subsystem for Digital Video Broadcasting via Satellite. In Digital video broadcasting for digital transmission for satellite applications, a powerful FEC sub-system is needed. FEC is based on inner LDPC (Low-Density Parity Check) codes concatenated with outer BCH (Bose ChaudhuriHocquenghem) codes, allowing Quasi Error Free operation close to the Shannon limit.
Features
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Irregular parity check matrix
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Layered Decoding
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Minimum sum algorithm
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Soft decision decoding
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BCH decoder works on GF (2m) where m=16 or 14 and corrects up to t errors, where t = 8, 10 or 12
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ETSI EN 302 307-1 V1.4.1 (2014-11) compliant
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Long and short frame lengths
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No error floor to QEF in Standard
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Easy to integrate within receiver all code rates and modulation orders
Benefits
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High performance
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High data rate
Deliverables
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Synthesizable Verilog
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System Model (Matlab)
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Verilog Test Benches Documentation
Applications
