Description and Features
DDR5 is full-featured, easy-to-use, synthesizable design, compatible with DDR5 JESD79-5 and JESD79-5 Rev1.40 (Draft) specification and DFI-version 5.0 Compliant. Through its DDR5 compatibility, it provides a simple interface to a wide range of low-cost devices. DDR5 IP is proven in FPGA environment. The host interface of the DDR5 can be simple interface or can be AMBA AHB, AMBA AHB-Lite, AMBA APB, AMBA AXI, AMBA AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or Custom protocol.

Features
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Supports DDR5 protocol standard JESD79-5 Specification.
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Compliant with DFI version 5.0 Specification.
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Supports up to 16 AXI ports with data width upto 512 bits.
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Supports controllable outstanding transactions for AXI write and read channels
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Supports in port arbitration and multi-port arbitration.
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Supports user programmable page policy. • Closed page policy • Open page policy
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Supports Error Checking and correction (ECC).
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Supports retry on ECC error, with retry limit user controllable.
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Supports high clock speeds in ASIC and FPGA.
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Supports low latency for write and read path.
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Supports reordering of transactions for higher performance.
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Supports up to 64GB device density.
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Supports X4, X8, X16 device types
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Supports all speed grades as per specification.
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Supports for Mode Registers programming.
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Supports for Sequential burst type.
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Supports Programmable burst lengths of 8,16 & 32.
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Supports for Programmable Write and Read latency.
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Supports Multiple Outstanding transaction.
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Supports In-port Arbitration using QoS.
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Supports Write Pattern Comand.
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Supports Auto precharge for Write, Read and Write pattern command.
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Supports for Write Data Mask.
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Supports Refresh modes and Global refresh counter.
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Supports Refresh management all command.
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Supports Refresh management same bank command.
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Supports 2N mode.
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Supports CRC and ECC for Write and Read Operations.
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Supports for Self-Refresh and Power Down operation.
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Supports for Precharge Command modes.
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Supports for Maximum Power Saving Mode (MPSM).
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Supports 1:4 and 1:2 Controller to DFI PHY frequency ratio.
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Supports Programmable clock frequency operation.
Deliverables
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The DDR5 interface is available in Source and netlist products.
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The Source product is delivered in Verilog. If needed VHDL, SystemC code can also be provided.
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Easy to use Verilog Test Environment with Verilog Testcases
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Lint, CDC, Synthesis, Simulation Scripts with waiver files
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IP-XACT RDL generated address map
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Firmware code and Linux driver package
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Documentation contains User's Guide and Release notes.