Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores

T2M Ethernet Ethernet 200/400G TSN MAC IP

Ethernet 200/400G TSN MAC IP

Description and Features

Ethernet 200/400G TSN MAC core is a full-featured, easy-to-use, synthesizable design that supports various Ethernet TSN IEEE standards. Through its Ethernet compatibility, it provides a simple interface to a wide range of low-cost devices. Ethernet 200/400G TSN MAC IP is proven in FPGA environment. It can also support a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.



  • Compliant with IEEE Standard 802.3-2018 Specification - Clause 117
  • Supports Preemption as per IEEE Standard 802.1Qbu and IEEE Standard 802.3br Interspersing Express Traffic
  • Supports timing synchronization as per IEEE Standard 1588-2008(PTP) and IEEE Standard 802.1AS(GPTP)
  • Supports Traffic Scheduling - IEEE Standard 802.1Qbv(Enhancement for Scheduled Traffic) and IEEE Standard 802.1Qav (Credit Based Shaping)
  • Supports class based flow control and class based FIFO to store each class, total 8 class - IEEE Standard 802.1Q
  • Supports Full duplex mode of operation
  • Ultra low latency and compact implementation
  • Supports MDIO (Clause 22 and Clause 45) Interface
  • Supports Programmable Inter Packed Gap(IPG) and Preamble length
  • Supports CDMII (64 bit) interface
  • FCS generation supported
  • Supports VLAN and jumbo frames as an option
  • Independent TX and RX Maximum Transmission Unit (MTU)
  • TSN features can be enabled/disabled independently
  • Cut-through support
  • Configurable Transmit and Receive FIFOs
  • Comprehensive statistics gathering
  • Supports 32bit AXI4 Stream for Packet data
  • In house UNH compliance tested
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to Microprocessor/Microcontroller devices


  • Customized licensing solution for businesses operating from a singular location, guaranteeing exclusive access.

  • Flexible licensing option for companies with operations spanning multiple sites, enabling broad deployment.

  • Permits integration of the IP Core into a single FPGA bitstream and ASIC, facilitating targeted implementation.

  • Provides unrestricted access to the IP Core for integration into an infinite number of FPGA bitstreams and ASIC designs, encouraging limitless creativity and scalability.


  • Verilog RTL design

  • Integrating waivers seamlessly into validation scripts to ensure comprehensive coverage of Linting, CDC analysis, and Synthesis

  • Providing exhaustive reports offering in-depth insights into Linting, CDC analysis, and Synthesis methodologies

  • Efficiently employing IP-XACT RDL to generate address maps with effectiveness

  • Merging firmware code and Linux drivers into a cohesive and unified package

  • Supplying detailed technical documentation covering all aspects comprehensively

  • Developing a Verilog Test Environment with intuitive integration of test cases for comprehensive testing