Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores

T2M › USB › USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP in 55LL

USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP in 55LL

Description

The combined PHY complies with the Peripheral Component Interconnect Express (PCIe), Serial ATA, USB, USB 3.0, and USB 2.0 interface protocols (USB High-speed and Full speed). Reduced power usage is made possible by supporting extra internal power gating, reference clock control, and PLL control. Because of the versatility of the previously mentioned low power mode option, the PHY is also particularly suitable for a variety of situations under different considerations of power consumption.

 

Features
  • Compatible with PCIe/USB3/SATA base Specification
  • Fully compatible with PIPE3.1 interface specification
  • Data rate configurable to 1.5G/2.5G/3G/5G/6G for different application
  • Support 16-bit or 32-bit parallel interface when encode/decode enabled
  • Support 20-bit parallel interface when encode/decode bypassed
  • Support flexible reference clock frequency
  • Support 100MHz differential reference clock input or output (optional with SSC) in PCIe Mode
  • Support Spread-Spectrum clock (SSC) generation and receiving from 5000ppm to 0ppm
  • Support programmable transmit amplitude and De-emphasis
  • Support TX detect RX function in PCIe and USB3.0 Mode
  • Support Beacon signal generation and detection in PCIe Mode
  • Support Low Frequency Periodic Signaling (LFPS) generation and detection in USB3.0 Mode
  • Support COMWAKE, COMINIT and COMRESET (OOB) generation and detection in SATA Mode
  • Support L1 sub-state power management
  • Support RX low latency mode in SATA operation mode
  • Support Loopback BERT and Multiple Pattern BIST Mode
  • HPC Plus 0.9V/1.8V 1P8M
  • ESD:HBM/MM/CDM/LatchUp2000V/200V/500V/100mA
  • Silicon Proven in SMIC 55LL

Deliverables

  • Graphic Data System II File with Layer Definitions

  • Layout Exchange Format illustrating Placement and Routing Views

  • .lib File containing Timing and Power Characteristics

  • Verilog Model depicting Circuit Behavioral Characteristics

  • Standard Delay Format (SDF) Timing applied to Netlist

  • Application Notes providing insights into Layout Optimization

  • LVS and DRC Verification Results Documentation

Application

  • PC
  • Television
  • Data Storage
  • Multimedia Devices
  • Recorders
  • Mobile Devices
Request Datasheet