Description and Features

An ultra-low-power programmable fractional-N at 600MHz, phase-locked loop (PLL) for frequency synthesis available at 22nm.

Features

• Integer Division
• High Stability
• Designed to be power-efficient
• Low Jitter
• Programmable Loop Filter
• Lock Detection
• Small Footprint designed to be compact    

Deliverables

• GDSII
• LVS Spice netlist
• Verilog model
• LEF for clock generator
• User Guidelines including:
•   integration guidelines
•   layout guidelines
•   testability guidelines
•   packaging guidelines
•   board-level guidelines