Description
An ultra-low-power programmable fractional-N at 600MHz, phase-locked loop (PLL) for frequency synthesis available at 22nm.
Features
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Integer Division
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High Stability
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Designed to be power-efficient
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Low Jitter
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Programmable Loop Filter
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Lock Detection
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Small Footprint designed to be compact
Deliverables
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GDSII
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LVS Spice netlist
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Verilog model
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LEF for clock generator
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User Guidelines including:
integration guidelines
layout guidelines
testability guidelines
packaging guidelines
board-level guidelines
