Production Proven, Complex Semiconductor IP Cores

IP Cores


T2M USB USB 3.0 PHY IP in 12FFC

USB 3.0 PHY IP in 12FFC

Description and Features

For auxiliary devices, a Universal Serial Bus (USB) transceiver is offered. The PHY complies with the requirements of UTMI, USB 2.0 PIPE, and USB 3.0 (USB SuperSpeed). The USB3.0 PHY IP transceiver is designed to consume little power and take up little space on the chip without compromising speed or data throughput. The USB3.0 PHY IP includes a full on-chip physical transceiver solution with Electrostatic Discharge (ESD) protection, a built-in self-test module with inbuilt jitter injection, and a dynamic equalization circuit to provide comprehensive support for high-performance designs. Several IP sources are supported by the USB3 MAC layer through the shared PHY interface (PIPE). Internal test monitoring and jitter are reduced by using constant power, built-in Jitter Injection Output, built-in Self-Test, and approved change of analogue circuit characteristics.

 

 

Features
  • Compliant with Universal Serial Bus 3.0 Specification

  • Supports 2.5GT/s and 5.0GT/s serial data transmission rate

  • Compliant with PIPE 3.0

  • Compliant with Universal Serial Bus 2.0 Specification

  • High-speed data transfer rate: 480 Mbps

  • Compliant with legacy USB 1.1

  • Full-speed data transfer rate: 12 Mbps

  • Compliant with UTMI 1.05 Specification

  • Operating Voltage: 1.1V and 3.3V

  • Support low jitter automatically calibrated oscillator for crystal-less mode

  • Support 125/250 MHz with 32/16-bit mode for USB 3.0

  • Support the Build-In-Self-Test (BIST) mode for low-cost TEG/ATE testing

  • Silicon Proven in TSMC 12FFC.

Deliverables

  • GDSII & layer map

  • Place-Route views (.LEF)

  • Liberty library (.lib)

  • Verilog behavior model

  • Netlist & SDF timing

  • Layout guidelines, application notes

  • LVS/DRC verification reports