Description
The MIPI Display Serial Interface (DSI) is an interface between a display or any other data interface, and a host processor baseband application engine. This interface is defined by the MIPI Alliance, which lays down a series of modules required in a MIPI compliant product. MIPI DSI Receiver is leveraged by mobile and high–speed serial applications as a controller for receiving video, command or user data, transmitted via MIPI DSI Transmitter over MIPI lines. It is sent to the next, higher level for subsequent processing. The MIPI DSI Receiver, along with MIPI DSI Transmitter and MIPI DPHY, provides a complete solution for MIPI DSI communication.
Features
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Programmable 1, 2 or 4 Data Lane Configuration.
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Compliant to mipi_DSI_specification_v1-2.pdf
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Forward and reverse LP communication (1 lane).
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1-bit ECC error detection and correction.
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2-bit ECC detection and Error reporting.
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CRC checking and error reporting.
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Supports all type of short and long packets
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Supports LP mode reverse communication.
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D-PHY error reporting.
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DSI Error checking and reporting.
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Supports reset trigger message.
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Configurable Virtual Channel.
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Pixel Interface: 16, 18 and 24 bits per pixel
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Operate in continuous and non-continuous clock modes.
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Command and Video Mode (Burst and Non-Burst mode) support
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Supports Stereoscopic image data.
Deliverables
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Configurable RTL Code
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HDL-based test bench and behavioral models
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Test cases
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Protocol checkers, bus watchers, and performance monitors
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Configurable synthesis shell
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Documentation
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Design guide
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Verification guide
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Synthesis guide
Benefits
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Highly modular and configurable design
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Layered architecture
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Active low async reset
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Clearly demarcated clock domains
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Extensive clock gating support
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Data lane count
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Color modes
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Pixel interface width
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Application Interface – Pixel or AXI
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Command FIFO depth
Applications
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Display Applications
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Imaging
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Video
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Smart TV
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Wearables
