The 12-bit 2.5 GSPS DAC IP Core employs a high-performance current steering architecture and provides an optional differential current output or differential voltage output. The bandgap and current source are included to provide a complete DAC. The DAC can be configured to adjust full-scale output range and has all the necessary calibration circuitry to provide excellent static and dynamic linearity performance. The DAC uses a proprietary architecture that reduces harmonic and intermodulation distortions at high output frequency and amplitudes. Our data converter (ADC and DAC) IP cores offer sampling rates from a few MSPS to over 20GSPS and resolutions ranging from 6 bits to 14 bits.
12bit Resolution
2.5 GSPS Update rate.
Functional from -40 deg C to 125 deg C
Reduces noise and power consumption.
Provides accurate charge transfer without the need for calibration.
Simplifies high-performance analog designs.
Deliverables
CDL netlists
Liberty timings
Verilog description
A full datasheet
An integration note.
Benefits
Excellent linearity
Compact area
High-performance low power
Complete subsystem with:
Bandgap reference
Support for I/Q and array configurations
Applications
5G Wireless Infrastructure
General purpose software defined radio.
High speed data acquisition systems
Cellular base station
Broadband communications
High-speed medical imaging
Wideband satellite receiver
Wireline Communication
Wireless Communication
Low Power IoT
