Production Proven, Complex Semiconductor IP Cores

IP Cores

T2M SerDes JESD204B Tx-Rx PHY IP in 55SP

JESD204B Tx-Rx PHY IP in 55SP

Description and Features

With the JESD204B Tx-Rx PHY IP interface, which fully supports the JESD204B synchronous serial interface, the JESD204B version specification is interoperable. Because of its compatibility, it provides a simple interface for a number of low-cost devices. The JESD204B PHY features full comprehensive transceiver capabilities in addition to solitary Tx and Rx.


  • Multiple lanes transceiver with data rate from 1Gbps to 16Gbps: Transceiver version including both receiver and transmitter

  • Transmitter only version available

  • 40bit/32bit/20bit/16bit selectable parallel data bus Independent per-lane power down control

  • Programmable transmit amplitude

  • Programmable 3-tap feed forward equalizer (FFE)

  • Embedded receiver equalization (CTLE and DFE) to compensate insertion loss

  • Build in self-test with multiple pattern generation and checker for production test

  • Flexible reference clock frequency range

  • Integrated LC-tank PLL and Ring OSC PLL

  • Integrated on-chip differential 100-ohm termination for reference clock

  • Low capacitance ESD structures

  • Integrated on-chip differential 100 ohm termination in TX and RX: Termination resistance auto calibration function (optional)

  • Support both Flip Chip Package and Wire Bonding Package

  • Testability: High Testability

  • Built-in pattern generator and checker including PRBS Internal serial loopback

  • Reliability: Lifetime: 10 years

  • Lifetime Average Temperature: up to 110 degC (include hot-spot)

  • Availability: 100%

  • ESD (HBM): over 2000V

  • ESD (CDM): over 250V

  • Latch-up: Satisfy JESD78 ClassII (Tj=125c), >100mA

  • Silicon Proven in UMC 55nm SP


  • Application Note / User Manual

  • Behavior model, and protected RTL codes

  • Protected Post layout netlist and Standard

  • Delay Format (SDF)

  • Frame view (LEF)

  • Metal GDS (GDSII)

  • Test patterns and Test Documentation


  • Low Power Consumption

  • Low Physical Area compared to market standard

  • Operating Temperature: ~ 110degrees

  • Layered and Structured architecture