Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores

T2M Ethernet 1G Ethernet Whitebox PHY IP

1G Ethernet Whitebox PHY IP

Description and Features

1G Ethernet PHY IP Core is available for licensing as a Whitebox IP, with unlimited usage and full modification rights granted to the customer, ensuring a high level of flexibility with the deliverables.

The GbE PHY IP for Giga 10/100/1000 Ethernet applications is a highly integrated solution including the Twisted Pair Physical Medium Dependent Sub-layer (TP-PMD, 100BASE-TX only), Physical Coding Sub-layer (PCS), and Physical Medium Attachment Layer (PMA). It supports 10BASE-T, 100BASE-TX, and 1000BASE-T protocols with a very low power consumption and area. The Media Access Control Layer (MAC) is connected to this GPHY via GMII (Giga Media Independent Interface) or via RGMII. It supports Unshielded Twisted Pair Category 5 Cable (UTP5), or UTP5/UTP3 cable. The Gigabit physical layer function is defined by IEEE 802.3ab and IEEE 802.3u.


  • IEEE 802.3-2008, IEEE 802.3az fully standards compliant

  • IEEE 1588-2008 support

  • BroadR-Reach™ support

  • Dual port MAC interface:

  • GMII (10/100/1000BASE-T)

  • MII (10/100BASE-T)

  • Auto-negotiation support

  • Automatic detection and correction of pair swaps (Auto-MDIX), pair skew and pair polarity

  • 6 different operating modes:

  • 1000BASE-T Full Duplex and Half Duplex

  • 100BASE-TX Full Duplex and Half Duplex

  • 10BASE-T Full Duplex and Half Duplex

  • Management interface

  • Baseline wander compensation

  • On-chip transmit wave-shaping

  • On-chip hybrid circuit

  • 10KB jumbo frames

  • Internal, external and remote loop back

  • Hardware configuration for default operation

  • Power down mode, interrupt support

  • IEEE 1500 support for SoC testing integration

  • LED indication: link mode, status, speed, activity and collision

  • Extracted from Production Chipset


  • Extensive Product Documentation

  • Verilog Model (A) for Simulation Purposes

  • Liberty Database (.db/.lib) for Synthesis, Timing Analysis, and Equivalence Verification

  • Design Verification with CTL/CTLDB Techniques

  • ATPG Utilizing SPF (STIL Procedure File)

  • Layout Exchange Format (LEF) for Automated Place and Route (APR)

  • Circuit Description Language (CDL) for Layout Versus Schematic (LVS) Alignment