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T2M › USB › USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP in 28HPC+

USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP in 28HPC+

Description

The combination PHY comprises of a Serial ATA (SATA) compliant with the SATA 3.0 Specification, a Peripheral Component Interconnect Express (PCIe) compliant with the PCIe 2.0 Base Specification with compatibility for the PIPE interface spec, and a USB compliant with the USB 3.0, USB 2.0 (USB High-speed and Full speed). Lower power usage is achieved by supporting more PLL control, reference clock control, and internal power gating control. Additionally, because the aforementioned low power mode option is configurable, the PHY is widely applicable for a variety of situations under different considerations of power consumption.

 

Features

  • Compatible with PCIe/USB3/SATA base Specification

  • Fully compatible with PIPE3.1 interface specification

  • Data rate configurable to 1.5G/2.5G/3G/5G/6G for different application

  • Support 16-bit or 32-bit parallel interface when encode/decode enabled

  • Support 20-bit parallel interface when encode/decode bypassed

  • Support flexible reference clock frequency

  • Support 100MHz differential reference clock input or output (optional with SSC) in PCIe Mode

  • Support Spread-Spectrum clock (SSC) generation and receiving from 5000ppm to 0ppm

  • Support programmable transmit amplitude and De-emphasis

  • Support TX detect RX function in PCIe and USB3.0 Mode

  • Support Beacon signal generation and detection in PCIe Mode

  • Support Low Frequency Periodic Signaling (LFPS) generation and detection in USB3.0 Mode

  • Support COMWAKE, COMINIT and COMRESET (OOB) generation and detection in SATA Mode

  • Support L1 sub-state power management

  • Support RX low latency mode in SATA operation mode

  • Support Loopback BERT and Multiple Pattern BIST Mode

  • HPC Plus 0.9V/1.8V 1P8M

  • ESD:HBM/MM/CDM/LatchUp2000V/200V/500V/100mA

  • Silicon Proven in TSMC 28HPC+

Deliverables

  • GDSII IC Layout Data with Layer Specifications

  • .LEF Files Illustrating Placement and Routing Views

  • Library of Timing and Power Models in .lib Format

  • Verilog HDL Representation of Circuit Behavior

  • Circuit Netlist Annotated with SDF Timing Constraints

  • Design Guidelines and Best Practices for Layout Implementation

  • Reports Confirming Layout Consistency and Compliance with Design Rules

Application

  • PC

  • Television

  • Data Storage

  • Multimedia Devices

  • Recorders

  • Mobile Devices

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