Production Proven, Complex Semiconductor IP Cores

IP Cores

T2M Ethernet Ethernet 50G PCS IP

Ethernet 50G PCS IP

Description and Features

Ethernet 50G PCS core is compliant with IEEE Standard 802.3.2018 Ethernet specification. Through its Ethernet compatibility, it provides a simple interface to a wide range of low-cost devices. Ethernet 50G PCS IP is proven in FPGA environment. It can also support a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.



  • Supports IEEE Standard 802.3.2018
  • Supports 50G BASE-R
  • Supports 50G BASE KR2/CR2
  • Supports 64b/66b encoding and decoding for transmit and receive path
  • Supports data scrambling on the transmit path and descrambling on the receive path
  • Supports Lane Distribution across 4/2 Lanes for 50Gpbs
  • Supports Block synchronization
  • Supports gearbox for various data width
  • Supports Alignment Marker insertion and removal
  • Support PCS Lane Deskew
  • Supports BIP-8 insertion on transmit path and checking on receive path per lane
  • Supports Bit Error Rate monitoring
  • Supports receiver Link fault status detection
  • Supports Loopback functionality
  • Supports for IEEE 802.3az Energy Efficient Ethernet.
  • Supports Configurable Management Interface (MDIO - Clause 45 / SOC Bus)
  • Supports PMA interface for the following data widths, • 32 • 40
  • Supports RS FEC as per clause 108 of IEEE Standard 802.3.2018
  • Optional support for Base-R FEC as per clause 74 of IEEE Standard 802.3.2018
  • Programmable PRBS32 and PRBS9 test pattern generators and error checker
  • Optional support for auto negotiation for backplane Ethernet as per clause 73 of IEEE Standard 802.3.2018
  • Optional support for link training as per clause 72 of IEEE Standard 802.3.2018
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to Microprocessor/Microcontroller devices


  • The Ethernet interface is available in Source and netlist products.
  • The Source product is delivered in plain text Verilog. If needed VHDL, SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files
  • IP-XACT RDL generated address map
  • Firmware code and Linux driver package
  • Documentation contains User's Guide and Release notes