Description
The D-PHY specification, version 1.2, is completely complied with by the MIPI D-PHY Analog TX IP Core. The Display Serial Interface and the MIPI Camera Serial Interface (CSI-2) are both compatible with it (DSI protocols). One clock lane and four data lanes make up this TX PHY. An analogue front end produces and receives electrical level signals, while a digital back end controls the I/O operations. automatic calibration for an inbuilt termination resistor A MIPI DSI PHY (MIPI TX DPHY), the D-PHY consists of a PLL, a Clock Lane, four Data Lanes, and a clock lane in addition to a D-PHY that may be used as a GPIO bank with a 5V tolerance.
Features
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Compliant to MIPI Alliance Standard for D-PHY specification Version 1.2
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Supports standard PPI interface compliant to MIPI Specification
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Supports synchronous transfer at high-speed mode with a bit rate of 80-2500 Mb/s
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Supports asynchronous transfer at low power mode with a bit rate of 10 Mb/s
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Supports ultra-low power mode, high-speed mode and escape mode
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Supports one clock lane and up to four data lanes
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Data lanes support transfer of data in high-speed mode
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Supports error detection mechanism for sequence errors and contentions
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Supports contention detection
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Configurable skew option for each Clock and Data lanes
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Testability for TX, RX and PLL
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Silicon Proven in GF 55LPe.
Deliverables
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GDSII & layer map
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Place-Route views (.LEF)
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Liberty library (.lib)
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Verilog behaviour model
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Netlist & SDF timing
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Layout guidelines, application notes
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LVS/DRC verification reports
