The DisplayPort v1.4 Tx PHY IP in 12FFC is a modernistic technology designed to be integrated into chip designs for various devices, including graphics cards, monitors, and laptops. Utilizing the 12nm FinFET Compact process technology, this IP strikes a balance between power efficiency and performance, making it an ideal solution for implementing DisplayPort 1.4 functionality and using of this DisplayPort 1.4 Tx PHY IP, device manufacturers can enable seamless transmission of high-quality video and audio signals in their products. This integration enhances the visual experience for users, offering advanced features and high-speed data transmission capabilities supported by DisplayPort 1.4. This transmitter PHY supports a wide range of bit rates, ranging from 1.62Gbps (RBR) to 5.4Gbps (HBR2), ensuring efficient data transmission in modern display technologies. It includes integrated features such as 100-ohm termination resistors with common-mode biasing, which improves signal integrity and this transmitter PHY incorporates an integrated equalizer with tunable strength, allowing for signal optimization over long cable lengths or challenging environments. The IP also offers configurable analog characteristics, including CDR bandwidth, equalizer strength, terminator resistance, BGR voltage, and regulator voltage. This flexibility enables customization to meet specific requirements and enhances compatibility with different system configurations. This DisplayPort 1.4 Tx PHY IP in 12FFC plays a vital role in advancing display technologies and enabling the development of futuristic devices across various industries. Its integration into chip designs empowers device manufacturers to deliver enhanced visual experiences to users while maintaining efficient data transmission capabilities.
eDP version 1.4a / DP version 1.4 compliant transmitter
Supports HDCP1.4 and HDCP2.2(Optional)
Supports Forward Error Correction (Optional)
Consists of configurable (4/2/1) link channels and one AUX channel
Supports 1.62/2.7/5.4/8.1Gbps (HBR3) bit rate and all recommended link rate (ie 2.16Gbps etc)
Supports main link operation with 1 or 2 or 4 lanes
Supports both Default and Enhanced Framing Mode
Supports SST mode
Supports video packet and audio packet (8ch max)
Supports both Normal and Alternate Scrambler Seed Reset
Supports E-EDID data reading via I2C-over-AUX transaction
Supports Video test pattern generator (compliant with DP link CTS v1.2)
Configuration registers programmable via AMBA interface
Silicon Proven in TSMC 12nm FFC
High-resolution and refresh rates support (4K, 5K, 8K, etc.) at various refresh rates (60Hz, 120Hz, 144Hz).
Multi-Stream Transport (MST) support for connecting multiple displays.
High Dynamic Range (HDR) support for improved colour gamut and contrast ratios.
Low power consumption for energy-efficient applications.
Integration-friendly design for easy integration into semiconductor chips or SoCs.
Deliverables
Verilog RTL or netlist source code for the LINK controller
Timing abstraction models suitable for synthesis and static timing analysis (STA)
Synthesis and physical layout timing constraints
Behavioral Verilog model, simulation test bench, execution scripts, and test stimuli
Physical design database
Guidelines for integration Reference software sample code
