Description and Features

The MIPI M-PHY Gear 4 IP is compatible with the most recent MIPI Feature Storage IP Solution SerDes PHY Product Brief Alliance M-PHY v4.1 Specification, UniPro v1.8 Specification, and Universal Flash Storage (UFS) v3.0 Specification. a high-bandwidth serial interface technology that was created especially for mobile applications to achieve decreased pin count and superior energy efficiency. It can support HS Gear4 rates of up to 11.6Gbps. The RMMI interface-compatible MIPI M-PHY Gear 4 IP supports the UniPro controller and UFS Controller. The MIPI M-PHY provides low-cost Build-In-Self-Test for dependable embedded system debugging and receiver ocular data monitoring (BIST).

Features

• Compatible with PCIe base Specification
• Full compatible with PIPE3.0 interface specification
• Independent channel power down control
• Implemented Receiver equalization Adaptive-CTLE to compensate insertion loss
• Support 16-bit/32bit parallel interface
• Support for PCIe gen1(2.5Gbps) and PCIe gen2(5.0Gbps)
• Support flexible reference clock frequency
• Support 100MHz differential reference clock input or output (with SSC optionally) in PCIe Mode
• Support Spread-Spectrum clock (SSC) generation and receiving from -5000ppm to 0ppm
• Support programmable transmit amplitude and Deemphasis
• Support TX detect RX function in PCIe Mode
• Support Beacon signal generation and detection in
• Production test support is optimized through high coverage at-speed BIST and loopback
• Integrated on-die termination resistors and IO Pads/Bumps
• Embedded Primary & Secondary ESD Protection
• ESD: HBM/MM/CDM/Latch Up 2000V/200V/500V/100mA
• Silicon Proven in TSMC 40LP

Deliverables

• Application Note / User Manual
• Behaviour model, and protected RTL codes
• Protected Post layout netlist and Standard Delay Format (SDF)
• Library (LIB)
• Frame view (LEF)
• Metal GDS (GDSII)
• Test patterns and Test Documentation