Description
The eSPI controller has a comprehensive feature set, is simple to use, can be synthesized, and is compliant with the eSPI standard protocol. It gives a variety of inexpensive devices a straightforward interface thanks to its eSPI compatibility. In an FPGA context, ESPI controller IP has been tested. The eSPI controller's host interface options include a basic interface, AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone, or a custom protocol. Verilog and VHDL both natively support eSPI Controller IP.
Features
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Compliant with eSPI base specification as defined in Enhanced Serial Peripheral Interface (eSPI) Specification rev.1.0.
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Supports Master and Slave Modes
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Supports Single, Dual and Quad modes
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Supports TX and RX operation as per specs
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Supports below transaction phases • Command Phase • Turn-Around Phase • Response Phase
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Supports baud rate selection
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Supports Slave triggered transaction
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Supports Power management Event
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Supports Interrupts and Alert
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Supports In-band reset
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Supports below multiple channels • Peripheral Channel • Virtual Wires Channel • OOB Message (Tunnelled SMBus) Channel • Run-time Flash Access Channel
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Various kind of Master and Slave errors detection and handling
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Supports CRC checking
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Fully synthesizable.
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Static synchronous design.
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Positive edge clocking and no internal tri-states
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Scan test ready
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Simple interface allows easy connection to Microprocessor/Microcontroller devices
Deliverables
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The eSPI CONTROLLER interface is available in Source and netlist products.
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The Source product is delivered in Verilog. If needed, VHDL and SystemC can also be provided
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Easy to use Verilog Test Environment with Verilog Testcases
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Lint, CDC, Synthesis, Simulation Scripts with waiver files
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IP-XACT RDL generated address map
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Firmware code and Linux driver package
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Documentation contains User's Guide and Release notes.
