Description and Features
The Ethernet 10G Verification IP is compliant with IEEE 802.3 Specification and verifies MAC-to-PHY and PHY-to-MAC layer interfaces of designs with a Ethernet 10G interface. It can work with SystemVerilog, Vera, SystemC, E and Verilog HDL environment. Ethernet 10G verification IP is developed by experts in Ethernet, who have developed ethernet products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a ethernet product. Ethernet 10G Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env Ethernet 10G Verification IP comes with optional Smart Visual Protocol Debugger which is GUI based debugger to speed up debugging.

Features
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Supports 10G as per specification IEEE 802.3-2018 • Supports XGMII(32 and 64 Width) • Supports XGMII_R(32 and 64 Width) • Supports XTBI (i.e Output of 8b/10b PCS) • Supports XAUI,RXAUI,DXAUI,RXTBI and 10GBASE-KX4 • Supports 10GBASE-KR with scrambler • Supports FEC for 10GBase-KR • Supports scrambler • Supports backplane auto-negotiation for 10GBase-KX4 and 10GBase-KR
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Supports USXGMII • Supports single port USXGMII as per specification 2.5 • Supports multi-port USXGMII as per specification 2.2
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XSBI Interface (16-bit)
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XSBI Interface (20-bit)
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Supports Link training
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Supports G.999.1 Interface
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Ethernet Verification IP comes with complete UNH Test suite
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Supports the Upper layer protocols
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Supports IP in IP and Supports Q in Q
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Full support for IEEE 802.1AZ (Energy Efficient Ethernet)
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Full support for IEEE 1588-2002 and IEEE 1588-2008
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PCS to Serdes interface supports all widths
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Supports CDR for serial protocols
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Supports WAN Interface Sublayer (WIS), type 10GBASE-W
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Supports MDIO slave and master model as per Clause 22 and Clause 45
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Supports Glitch insertion and detection
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Supports all types of TX and RX errors insertion/detection at each layer.
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Under and oversize frame. • CRC errors, Framing errors, Pause frame errors • Disparity and Auto-negotiation errors • Invalid code group insertion • Invalid /K/ characters insertion • Invalid AN sequence error insertion • Missing /K/ characters for packet boundries.
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Comes with Tx BFM, Rx BFM, and Monitor
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Monitor supports detection of all protocol violations
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Supports Pause frame generation and detection
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Built in coverage analysis
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Callbacks in master and slave for various events
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Status counters for various events in bus
Deliverables
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Complete regression suite containing all the testcases.
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Examples showing how to connect various components, and usage of TX,RX BFM and Monitor.
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Detailed documentation of all class, task and function's used in verification env.
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Documentation also contains User's Guide and Release notes.