Production Proven, Complex Semiconductor IP Cores

IP Cores

T2M Verification IPs JESD204 VIP


Description and Features

JESD204 (Serial Interface for Data Convertors) is the serial communication protocol developed used with ADC and DAC. JESD204A/B/C VIP can be used to verify transmitter or Receiver device following the JESD204 basic protocol as defined in JESD204. It can work with Verilog HDL environment and works with all Verilog simulators that are support SystemVerilog. JESD204 Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env JESD204 Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.



  • Follows JESD204 specification JESD204A, JESD204B and JESD204C
  • Supports Transmitter and Receiver Mode.
  • Supports up to 32 lanes.
  • Supports 32bit data width per converter.
  • Supports up to 256 converters per transmitter & receiver BFM.
  • Scrambler can be enabled or disabled.
  • Supports 8b/10b link layer functions.
  • Supports 64b/66b link layer functions based on IEE802.3 Clause 49 and JESD204C.
  • Supports 64b/80b link layer functions with fill bit encoding based on IEEE802.3 clause 49 and JESD204C.
  • Supports Forward Error Correction (FEC) and command channel.
  • Supports following cyclic redundancy checks (CRC) encoding in JESD204C.
  • CRC-3
  • CRC-12
  • Supports single block, Multi block and extended multi block.
  • Provides error injection and error detection with a wide variety of error types. Which includes,
  • Invalid code group insertion
  • Disparity errors
  • CRC errors
  • Sync error insertion
  • Lane skew insertion
  • FEC errors
  • Scrambler error insertion
  • Supports constraints Randomization.
  • Functional coverage to cover each and every feature of the JESD204 specification.
  • Test suite to test each and every feature of JESD204 specification.
  • Call-backs monitor, transmitter and receiver for various events.
  • Status counters for various events on bus.


  • Complete regression suite containing all the JESD204 testcases.
  • Examples showing how to connect various components, and usage of Transmitter, Receiver and Monitor.
  • Detailed documentation of all class, task and functions used in verification env.
  • Documentation contains User's Guide and Release notes