To support increased applications, PCIe 3.0 PHY IP provides a low-power, multi-lane, high-performance design. A full variety of PCIe 3.0 Base applications are supported by the PCIe 3.0 IP, which also complies with the PIPE 4.3 specification. To enable PCIe 3.0 traffic at 8Gbps, the IP combines high-speed mixed signal circuits. With a transfer throughput of 5.0 Gbps for PCIe 2.0 and 2.5 Gbps for PCIe 1.0, it is backwards compatible. The PCIe 3.0 IP may satisfy the needs for various channel circumstances since it supports both TX and RX equalisation approaches.
Compliant with PCIe 3.0 Base Specification
Compliant with PIPE 4.3
Supported data transfer rate: 2.5 GT/s, 5.0 GT/s and 8.0 GT/s
Supported physical lane width: x4
Supported parallel interface: 32-bit
Supported input reference clock: 100 MHz
Supported parallel interface data clock: 62.5 MHz, 125 MHz, and 250 MHz
Supporting low power operation with configurable setting in power state P1/P2/L1 PM Substates:PLL control, reference clock control, and embedded power gating control
Silicon Proven in TSMC 22ULP
Operating Voltage: 0.9V, 0.95V, 1.2V and 1.8V
Providing robust testability by low-cost Build-In Self-Test (BIST) via near-end analog and external loopback interface as well as far-end analog/digital loopback interface
Deliverables
GDSII & layer map
Place-Route views (.LEF)
Liberty library (.lib)
Verilog behaviour model
Netlist & SDF timing
Layout guidelines, application notes
LVS/DRC verification reports
