Description and Features
The HDMI receiver PHY (Physical layer), a single-port IP core, complies with all the specifications of HDMI 1.4. This HDMI RX PHY provides a straightforward system LSI solution for consumer electronics like HDTV and supports TMDS rates between 25MHz and 225MHz. The HDMI receiver link IP core and PHY work together most efficiently. All of the Fab/Nodes listed below have undergone Silicon Proving: Link Controller for an HDMI receiver that strictly adheres to HDMI 1.4a requirements (GF, Samsung, TSMC, UMC, SMIC, STMicro). This provides a straightforward system-onchip (SOC) implementation for consumer electronics including HD-TVs and AV receivers. It functions best when combined with our complementary HMDI receiver PHY IP core. The fundamental operations of HDMI can be changed to suit needs.
Features
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HDMI version 1.4 compliant receiver
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Supports DTV from 480i to 1080i/p HD resolution
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Supports 24bit, 30bit and 36bit color depth per pixel
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HDMI version 1.4a, HDCP revision 1.3 and DVI version 1.0 compliant receiver
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Supports DTV from 480i to 1080i/p HD resolution, and PC from VGA to UXGA
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Supports 3D video format specified in HDMI 1.4a specification
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Programmable 2-way color space converter
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Compliant with EIA/CEA-861D
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Deep color supported up to 16bit per pixel
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xvYCC Enhanced Colorimetry
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All packet reception including Gamut Metadata Packet
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Supports RGB, YCbCr digital video output format including ITU.656
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24/30/36/48bit RGB/YCbCr 4:4:4
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16/20/24bit YCbCr 4:2:2
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8/10/12bit YCbCr 4:2:2 (ITU.601 and 656)
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48 bit mode is not supported in 1080p
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Supports standard SPDIF output for stereo or compressed audio up to 192KHz
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Support PCM, Dolby digital, DTS digital audio output through 4bits I2S up to 8 channel
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IEC60958 or IEC61937 compatible
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1bit audio format (Super Audio CD) output
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High-bitrate compressed audio formats output
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Slave I2C interface for DDC connection
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Configuration registers programmable via synchronized parallel interface
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Interface to external HDCP key storage
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Integrated cable terminator
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Adaptive equalizer for cable
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Adjustable analog characteristics
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PLL band width
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VCO gain, BGR voltage
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Cable terminator resistance value
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DLL digital filter characteristics
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Integrated Audio PLL
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3.3V/2.5V/1.0V power supply
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Silicon Proven in ST 28FDSOI.
Deliverables
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Datasheet and integration guideline
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GDSII or Phantom GDSII
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Layer map table
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CDL netlist for LVS
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Verilog behavior model
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Liberty timing model
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DRC/LVS/ERC results
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Configurable RTL Code
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HDL based test bench and behavioral models
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Test cases
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Configurable synthesis shell
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Documentation
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Design Guide
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Verification Guide
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Synthesis Guide
