Octal SPI is the serial synchronous communication protocol. It includes an extensive test suite covering most of the possible scenarios. It performs all possible protocol tests in a directed or a highly randomized fashion which adds the possibility to create the widest range of scenarios to verify the DUT effectively. It can work with Verilog HDL environment and works with all Verilog simulators that are support SystemVerilog. Octal SPI (Serial Peripheral Interface) Verification IP issupported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env Octal SPI (Serial Peripheral Interface) Verification IP comes with optional Smart Visual Protocol Debugger which is GUI based debugger to speed up debugging.
Follows Octal SPI basic specification as defined in Flash memory.
Supports Master and Slave Mode.
Supports Serial Peripheral Interface -- Mode 0
Supports below Protocol modes • Single I/O and Octa I/O • Support DTR (Double Transfer Rate) Mode
Supports clock frequency up to • Single I/O mode: 133MHz • Octa I/O mode: 133MHz
Supports below Input Data Format • SPI: 1-byte command code • OPI: 2-byte command code
Supports below Advanced Security Features
Block lock protection
Advanced Sector Protection (Solid and Password Protect)
Supports below Additional 8K bit security OTP • Features unique identifier • Factory locked identifiable, and customer lockable