This eDisplayPort v1.4 Tx PHY IP in 22ULP is an advanced semiconductor intellectual property (IP) core meticulously crafted for ultra-low-power (22nm ULP) integrated circuits. This core serves as a gateway for transmitting high-fidelity video and audio signals, seamlessly adhering to the eDisplayPort v1.4 standard to ensure impeccable compatibility with contemporary display technologies. Distinguished by its ingenuity and adept power management, this IP core stands as the quintessential choice for energy-efficient devices. It empowers these devices with flawless, high-performance display connectivity, all while ensuring minimal power consumption. The eDP Tx PHY is tailored for chips engaging in eDP/DP data exchange, masterfully operating within the confines of low power usage. Its centrepiece is a multi-gigabit transmitter macro, boasting speeds of up to 8.1 Gbps for data transmission, optimally balancing power, and die size considerations. This macro seamlessly integrates into video systems, offering both ease of fabrication and implementation. The AUX channel, a half-duplex, bidirectional conduit consisting of a single differential pair, adds to the versatility by supporting a bit rate. The eDP Tx PHY IP has the ability to optionally incorporate a cipher function for High-bandwidth Digital Content Protection (HDCP), enabling the secure transmission of audiovisual content.
Support data rate of main link : 0.6Gbps~4.0Gbps
Utilize per-lane 10/20bit parallel interface for main link
Support Spread Spectrum clock generation: -
5000ppm@31.5KHz
AC coupling
One shared PLL for all the lanes
Individual power down for each lane
Support 0~9dB programmable 2-tap FFE (feed forward equalization) for main link
AUX channel included
Embedded BIST
Support wire bonding and flip chip package
Reliability
Life Time : 10 years, with Average
Temperature up to 110 degC
Availability : 100%
ESD (HBM) : over 2000V
Silicon Proven in TSMC 22nm ULP
Deliverables
GDSII & layer map
Place-Route views (.LEF)
Liberty library (.lib)
Verilog behaviour model
Netlist & SDF timing
Layout guidelines, application notes
LVS/DRC verification reports
