Production Proven, Complex Semiconductor IP Cores

IP Cores

T2M DisplayPort eDisplayPort v1.4 Tx PHY IP in 22ULP

eDisplayPort v1.4 Tx PHY IP in 22ULP

Description and Features

eDP/DP Tx PHY is designed for chips that perform eDP/DP data communication while operating at low power consumption. The main link is a multi-gigabit transmitter macro which enable speed up to 4.0Gbps data transmitter with optimized power and die size, also it can be easily fabricated and implemented in a video system. The AUX channel is a half-duplex, bidirectional channel consisting of one differential pair, supporting the bit rate of about 1Mbps.


  • Support data rate of main link : 0.6Gbps~4.0Gbps

  • Utilize per-lane 10/20bit parallel interface for main link

  • Support Spread Spectrum clock generation: -

  • 5000ppm@31.5KHz

  • AC coupling

  • One shared PLL for all the lanes

  • Individual power down for each lane

  • Support 0~9dB programmable 2-tap FFE (feed forward equalization) for main link

  • AUX channel included

  • Embedded BIST

  • Support wire bonding and flip chip package

  • Reliability

  • Life Time : 10 years, with Average

  • Temperature up to 110 degC

  • Availability : 100%

  • ESD (HBM) : over 2000V

  • Silicon Proven in TSMC 22nm ULP


  • GDSII & layer map

  • Place-Route views (.LEF)

  • Liberty library (.lib)

  • Verilog behaviour model

  • Netlist & SDF timing

  • Layout guidelines, application notes

  • LVS/DRC verification reports