Description
The SDIO Host IP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The SDIO Host IP can be implemented in any technology. The SDIO Host IP core supports the SD Host Controller Specification and supporting standards. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, APB, AXI, OCP, Wishbone, VCI, Avalon PLB, Wishbone, Tilelink or custom buses. The SDIO Host IP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The SDIO Host IP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.
Features
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Compliant with SD Host Controller Specification version 6.0
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Compliant with SDIO Physical Specification version 6.10
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Compliant with Part E1 SDIO specification 4.10
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Supports SDMA, ADMA2 and ADMA3 modes
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Supports all features of Part 1 eSD(Embedded SD) addendum version 2.10
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Supports SD Memory, SD I/O card, Combo card
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Supports 1-bit, 4-bit, 8-bit SD bus mode and SPI Bus mode
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Supports all commands/response types
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Supports SDR12, SDR25 ,DDR50, SDR 50 and SDR104 modes
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Supports Single byte, Single block , Multi –block(finite and infinite) transfers
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Supports command queue
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Supports suspend and resume
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Supports read wait
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Supports card detection
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Fully synthesizable
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Static synchronous design
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Positive edge clocking and no internal tri-states
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Scan test ready
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Simple interface allows easy connection to microprocessor/microcontroller devices
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Optionally UHS - II support can be added
Deliverables
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RTL design in Verilog.
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Lint, CDC synthesis script with waiver files.
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Lint, CDC synthesis reports.
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IP-XACT RDL generated address map.
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Firmware code and Linux driver package.
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Technical documentation in greater detail.
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Easy to use Verilog test environment with Verilog test cases.
