8G Multiprotocol Serdes IP in 14SFP

Description and Features

Features

• Area: ~0.3mm2 per-lane
• Silicon Proven in SMIC14SF+/SF++ with 0.8V and 1.8V power supply
• Support for SATA3(6.0Gbps) and PCIe3(8.0Gbps)
• Backward compatible with 1.5Gbps, 3.0bps for SATA
• Backward compatible with 2.5Gbps and 5Gbps for PCIe
• Full compatible with PIPE4 interface specification
• 20bit/16bit selectable parallel data bus
• Independent channel power down control
• Programmable transmit amplitude and FFE
• Implemented Receiver equalization Adaptive-CTLE and DFE to compensate insertion loss
• Production test support is optimized through high coverage at-speed BIST and loopback
• Integrated on-die termination resistors and IO Pads/Bumps
• Support receiver detection, OOB/Beacon signal generation and detection
• Support Spread Spectrum clock generation(optional) and receiving
• Embedded Primary & Secondary ESD Protection HBM/MM/CDM/Latch-Up 2000V/200V/500V/100mA

Deliverables

• Application Note / User Manual
• Behavior model, and protected RTL codes
• Protected Post layout netlist and Standard
• Delay Format (SDF)
• Synopsys library (LIB)
• Frame view (LEF)
• Metal GDS (GDSII)