Description and Features
This ultra high speed wide-band Analog-to-Digital Converter is based on 16 Time Interleaved Pipeline sub-ADC followed by a digital correction algorithm for gain, offset and skew correction. The differential input is terminated by a 100 Ohms resistor (100 Ohms differential) and followed by an input buffer driving the sub-ADC. The signal amplitude is 1Vpp differential. The analog source driving the ADC should be ac-coupled to the input pins with two external capacitors of 1nF minimum. The input common mode is generated internally.
Features
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14-bit Time-Interleaved Pipeline ADC
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4.32GSps Sampling Rate
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60dBFS SNR (9.7 ENOB) with 54MHz
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External AC coupling for the input signal
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Two power supplies: 1.8V for analog & 1.0V for digital compensation
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1.0Vpp differential full-scale input
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Buffered analog inputs
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Input signal bandwidth: 54MHz to 1794MHz
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Power down mode
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16x14bits data output at 270 MHz (4.32GHz/16)
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Data ready output at 270MHz
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Silicon Proven : 28FDSOI
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Extracted from a production DOCSIS Tuner STB chip
Deliverables
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Source Code Delivery including : Unlimited Usage and Rights to Modify
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Technical documents
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Design Guide
Application
