MIPI I3C Verification IP provides a smart way to verify the MIPI I3C bi-directional two-wire bus. The MIPI I3C Verification IP is fully compliant with MIPI I3C version 1.0, Draft version 1.1 and HCI version 1.0, Draft version 1.1 and 2.0 specifications. MIPI I3C Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env MIPI I3C Verification IP comes with optional Smart Visual Protocol Debugger which is GUI based debugger to speed up debugging.
Compliant with MIPI I3C version 1.1 specification.
Full MIPI I3C Master and Slave functionality
Two wire serial interface up to 12.5 MHz
Supports all topologies. • Multi and single Master-Multi Slave • Multi and single Master-Single Slave
Supports Single Data Rate (SDR) Messaging. • I3C Coding SDR • I3C Coding SDR with CCC Directed and broadcasted addressing
Supports High Data Rate (HDR) Messaging. • HDR-Dual Data Rate Mode (HDR-DDR) • HDR-Ternary Symbol Legacy Mode (HDR-TSL) • HDR-Ternary Symbol Pure-Bus Mode (HDR-TSP) • HDR Bulk Transport Mode (HDR-BT)
SDR Based ML Frame Formats • SDR-ML DUAL & QUAD Coding
HDR-DDR Based ML Frame Formats • DDR-ML DUAL & QUAD Coding
HDR-TSP Based ML Frame Formats • TSP-ML DUAL & QUAD Coding
HDR-BT Based ML Frame Formats • BT-ML DUAL & QUAD Coding
Support for Device to Device(s) Tunneling.
In-Band Interrupt support
Hot-Join request support • Support for all I3C Common Command Codes • Supports CCC framing in HDR-DDR/TSL/TSP/BT modes. • Supports HDR-DDR ML Coding and interoperability for CCC’s.
PIO Interface support (PIO Mode) • Command Queue Operation • Response, IBI Queue Operation
Auto-Reject for In-Band Interrupt and Hot-Join (NACK and directed DISEC CCC to disable)