The JESD 204B PHY IP is highly optimized and silicon agnostic implementation of the JEDEC JESD204B standard targeting any ASIC, FPGA and ASSP technologies. The solution defaults provide line-speed up to 12.5 Gbps per lane while guaranteeing data alignment and synchronization. The enables quick and reliable deployment of both the Transmitter (TX) and the receiver (RX) and comes optionally and tightly integrated transport layer option, that can dynamically be configured to handle any Multiple-Converter Device Alignment, Multiple Lanes (MCDA-ML) requirements. The IP-core is Silicon proven heavily tested In UVM regression environment and has been interoperability tested with key ADC/DAC providers and leading Serdes/PHY solutions .
Widest feature set available in market.
Scrambling and de-scrambling Included.
High performance transport layer support.
Build in test functions
UVM regression tested
Interoperability tested with leading PHY/Serdes vendors
Solid documentation including integration guide
Easy to use RTL test environment
Targeting any RTL implementation like ASICs, ASSPs and FPGAs.