RapidIO EndPoint interface provides full support for the RapidIO EP synchronous serial interface, compatible with RapidIO Interconnect 2.2 specification. Through its RapidIO EP compatibility, it provides a simple interface to a wide range of lowcost devices. RapidIO EP IP is proven in FPGA environment. The host interface of the RapidIO EP can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
Compliant with RapidIO Interconnect 2.2 specification
Supports all Capability Registers (CARs) and Configuration and Status Registers (CSRs)
Supports high link utilization and low latency
Supports efficient receive and transmit buffering scheme
Supports 34-bit addressing
Supports 8-bit device ID
Supports programmable source ID on all outgoing packets
Supports request class transactions: NREAD and ATOMIC set/clr/inc/dec/test and swap for readmodify-write operations
Supports write class transactions: NWRITE, NWRITE_R
Supports the Maintenance read request and Maintenance write request transactions
Supports Doorbell and Data Message class transactions
Supports streaming write class transactions: SWRITE
Supports the Continuous packet transactions
Supports the Parallel packet transactions
Supports the below physical layer features
o 1x/2x/4x serial lane support with integrated transceivers
o Supports per-lane speeds of 1.25, 2.5, 3.125, 5.0 and 6.25Gbaud
o Receive/Transmit packet buffering and error detection
o Automatic freeing of resources used by acknowledged packets
o Automatic retransmission of retried packets
Supports interrupt for each error detection and for complete serial message reception
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple interface allows easy connection to microprocessor/microcontroller devices.
The RapidIO EndPoint interface is available in Source and netlist products.
The Source product is delivered in plain text Verilog. If needed VHDL, SystemC code can also be provided.
Easy to use Verilog Test Environment with Verilog Testcases
Lint, CDC, Synthesis, Simulation Scripts with waiver files
IP-XACT RDL generated address map
Firmware code and Linux driver package
Documentation contains User's Guide and Release notes.