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Semiconductor IP Cores

T2M › PCI Express › PCIe 3.0 Controller IP

PCIe 3.0 Controller IP

Description

The PCIe Gen3 Controller is adaptable and expandable for ASIC and FPGA integration. It adheres to PCI Express 3.1/3.0 specifications, along with the PHY Interface for PCI Express (PIPE) specification and the AMBA® AXI™ Protocol Specification. It can be customized to support endpoint, root port, and dual-mode topologies, facilitating various usage scenarios, and provides a customizable, versatile AMBA AXI interconnect interface to users.

Delivered in Verilog RTL format, the PCIe Controller IP can be deployed in ASIC or FPGA environments. Validation of the PCIe Controller IP is conducted using FPGA. The core encompasses RTL code, test scripts, and a test environment for comprehensive simulation.

Features
  • Compliant with PCIE 1.0/2.0/3.0/4.0/5.0 Specifications
  • Full PCIE Controller functionality
  • Supports PIPE interface.
  • Compatible with Gen1,2,3,4 and 5
  • Supports following BFM modes
  • o Root Complex
  • o Endpoint
  • Supports queuing for 8 Virtual Channels with configurable depth Supports up to 8 Traffic Classes
  • Supports multi-function Configurable TC to VC queue mapping
  • Supports full link speed and width negotiation up to 8 Lanes
Benefits
  • Fully compliant, silicon-proven core
  • Comes with Verilog test bench and option to buy full advanced System Verilog Test bench
  • Support directly from engineer who designed the code.
  • Based on RMM (Re Use Methodology Manual guidelines)
  • Supports all the Synthesis tools.
Applications
  • PC
  • Digital TV
  • Set-top boxes
  • Enterprise computing, storage area networks, networking switches, and routers
  • Wireless and mobile devices
  • Industrial, automotive, and IoT
  • Embedded systems
  • Graphics devices
  • Laptops
  • Workstations
  • Servers
Deliverables
  • RTL design in verilog
  • Technical documentation in greater detail
  • Easy to use Verilog Test Environment with Verilog Test cases.
  • Digital Digital Digital lP controller with UVM VIP counterpart and relatable testbench components and all documentations
  • Hardware validation platforms with full compliance testing support and error scenario support
  • Bit file for digital IP controllers for any type of platforms

 

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