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T2M › HDMI › HDMI 1.3 Tx PHY IP in 40LP

HDMI 1.3 Tx PHY IP in 40LP

Description

HDMI transmitter PHY (Physical layer) IP core which is fully compliant with HDMI 1.3 specification. The HDMI TX PHY supports from 25MHz to 250MHz pixel clock, and offers a simple implementation for system LSI for consumer electronics like DVD player/recorder and camcorder. It is Silicon Proven in many Fab/Nodes including: (TSMC, UMC, SMIC, GF, Samsung, STMicro). HDMI Transmitter Link IP Core supporting the standard of HDMI 1.3a which will be quickly implemented into SoC of consumers' product (HD-TV, AV receiver... etc.). The best performance, efficiency and characteristic of HDMI Rx IP can be realized when it is connected to HDMI Transmitter PHY IP. HDMI Tx IP can be customized to meet customer specific requirement.

 

Features

  • HDMI version 1.3a compliant transmitter

  • HDMI version 1.3a, HDCP revision 1.2 and DVI version 1.0 compliant transmitter

  • Supports DTV from 480i to 1080i/p HD resolution, and PC from VGA to UXGA

  • Programmable 2-way color space converter

  • Compliant with EIA/CEA-861D

  • Deep color supported up to 12bit per pixel.

  • xvYCC Enhanced Colorimetry

  • Gamut Metadata transmission

  • Supports RGB, YCbCr digital video input format includes ITU.656

  • 36bit RGB/YCbCr 4:4:4

  • 16/20/24bit YCbCr 4:2:2

  • 8/10/12bit YCbCr 4:2:2 (ITU.601 and 656)

  • Supports standard SPDIF for stereo or compressed audio up to 192KHz

  • Support PCM, Dolby digital, DTS digital audio transmission through 4bits I2S up to 8 channel

  • IEC60958 or IEC61937 compatible

  • 1bit audio format(Super Audio CD)

  • High-bitrate compressed audio formats

  • Master I2C interface for DDC connection

  • Configuration registers programmable via parallel interface

  • Wide range channel speed up to 2.2Gbps

  • Programmable PLL characteristics, channel delay, and transmitter pre-emphasis rate

  • Supports DTV from 480i to 1080i/p HD resolution

  • Supports 24bit, 30bit and 36bit color depth per pixel

  • Integrated cable terminator

  • Adaptive equalizer for cable

  • Adjustable analog characteristics

  • PLL band width

  • VCO gain

  • BGR voltage

  • Cable terminator resistance value

  • DLL digital filter characteristics

  • Integrated Audio PLL

  • 3.3V/2.5V/1.0V power supply

  • GLOBAL FOUNDRIES 65nm (C65G) process

  • Silicon Proven in TSMC 40LP

Deliverables

  • Datasheet and Integration guideline

  • GDSII or Phantom GDSII

  • Layer map table

  • CDL netlist for LVS

  • Verilog behavior model

  • Liberty timing model

  • DRC/LVS/ERC results

  • Configurable RTL Code

  • HDL based test bench and behavioral models

  • Test cases

  • Configurable synthesis shell

  • Documentation

  • Design Guide

  • Verification Guide

  • Synthesis Guide

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