The eCPRI Verification IP is fully compliant with eCPRI Specification V2.0 and verifies eCPRI interfaces. It includes an extensive test suite covering most of the possible scenarios. It performs all possible protocol tests in a directed or a highly randomized fashion which adds the possibility to create the widest range of scenarios to verify the DUT effectively. eCPRI Verification IP is supported natively in System Verilog, VMM, RVM, AVM, OVM, UVM, Verilog, System C, VERA, Specman E and non-standard verification env eCPRI Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
Compliant with eCPRI Specification V2.0.
Complete eCPRI Tx/Rx functionality.
Supports the eCPRI layer of the eCPRI specification.
Supports the following message types. • IQ Data • Bit sequence • Real time control data • Generic data transfer • Remote memory access • One way Delay Measurement • Remote reset • Event Indication • IWF start-up • IWF operation • IWF mapping • IWF delay control • Vendor Specific
Supports Control and Management data transfer.
Supports data transfer through Ethernet/UDP/IP Interfaces.
Full support for IEEE 1588-2008 and IEEE 1588-2019
Supports delay management.
Supports 8B/10B line coding
Supports insertion of scrambler errors.
Detects and reports all the errors in Ethernet and CPRI layer
Glitch insertion and detection.
Monitors, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
Supports constraints Randomization.
Status counters for various events on bus.
Supports bus accurate timing and timing checks.
Callbacks in Master, Slave and Monitor for user processing of data.
eCPRI Verification IP comes with complete test suite to test every feature of eCPRI specification.
Functional coverage for complete eCPRI features.
Complete regression suite containing all the eCPRI testcases.
Examples showing how to connect various components, and usage of Master,Slave and Monitor.
Detailed documentation of all class, task and functions used in verification env.
Documentation contains User's Guide and Release notes