Description and Features

The Ethernet 1G PCS IP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The Ethernet 1G PCS IP can be implemented in any technology. The Ethernet 1G PCS IP core supports the Ethernet protocol standard of IEEE 802.3.2018 specification. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses . The Ethernet 1G PCS IP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The Ethernet 1G PCS IP is validated using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.

Features

• Supports PCS functionality compliant with IEEE Standard 802.3.2018 Clause 36
• Supports TBI Interface Supports 10/100/1000M and SGMII
• Supports Frame encapsulation at Transmit PCS and de capsulation at Receive PCS
• Supports synchronization on Receive PCS
• Supports generation of carrier sense and collision detection to GMII Interface Supports IEEE Standard 802.3.2018 Clause 37 Auto negotiation
• Supports IEEE Standard 802.3az Energy Efficient Ethernet(EEE)
• Supports Loopback Functionality
• Supports Configurable Management Interface (MDIO (Clause 22) Interface / SOC Bus)
• Supports Transmit and Receive Rate Adaptation in SGMII Interface Optional support for Auto negotiation with Next page
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple interface allows easy connection to Microprocessor/Microcontroller devices

Deliverables

• RTL design in Verilog
• Lint, CDC, Synthesis Scripts with waiver files
• Lint, CDC, Synthesis Reports
• IP-XACT RDL generated address map
• Firmware code and Linux driver package
• Technical documentation in greater detail
• Easy to use Verilog Test Environment with Verilog Testcases