Description and Features
This PHY IP supports both USB 3.2 Gen1 & Gen2. By providing a full on-chip physical transceiver solution with Electro Static Discharge (ESD) protection, an integrated self-test module with built-in jitter injection. This USB 3.2 Gen2 PHY IP implements USB3.2 Gen2 transceiver and can be used as host and device. PHY IP supports USB3.2 Gen2 high speed data rate up to 10Gbps with integrated mixed signal circuit, also supports Gen1 5Gbps data rate.
Features
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Support PHY interface (PIPE4.3) enables multiple IP sources for USB3 MAC layer
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Supports 5.0Gbps and 10Gbps serial data transmission rate
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Supports 16-bit or 32-bit parallel interface
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Data and clock recovery from serial stream
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Support 8b/10b encoder/decoder (Gen1), 128/132 encoder/ decoder (Gen2) and error indication
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Tunable receiver detection to detect worse case cables
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Low Frequency Periodic Signaling (LFPS) transmission and reception
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Support SSCG function to reduce EMI effects with tunable down-spread amplitude
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Selectable TX margining, TX de-emphasis and signal swing values
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Built-in-self-test with internal Loopback test option
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Programmable analog circuit parameter adjustment and internal test control
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Compliant with USB3.2 Gen2 base specification
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Silicon Proven in TSMC 28HPC+
Deliverables
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GDSII & layer map
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Place-Route views (.LEF)
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Liberty library (.lib)
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Verilog behavior model
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Netlist & SDF timing
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Layout guidelines, application notes
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LVS/DRC verification reports
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Test patterns and Test Documentation
