Description
SAE J1850 interface provides full support for the SENT SAE J1850 synchronous serial interface, compatible with SAE J1850-2015 standard. Through its SAE J1850 compatibility, it provides a simple interface to a wide range of low-cost devices. SAE J1850 IP is proven in FPGA environment. The host interface of the SAE J1850 can be simple interface or can be AMBA APB, AMBA AHB, AMBA AHB-Lite, AMBA AXI, AMBA AXI-Lite, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol. SAE J1850 IP is supported natively in Verilog and VHDL.
Features
-
Compliant with SAE J1850-2015 Specifications
-
Full SAE J1850 functionality
-
Supports Type0,1,2,3 frame formats
-
Supports Hardware CRC as per specs
-
Supports multi byte transmit and reception
-
Supports IRQ after frame transmission
-
Supports both VPW and PWM Bus symbols
-
Supports BREAK symbol generation
-
Supports Collision Detection
-
Dedicated Register for Symbol Timing Adjustments
-
Fully synthesizable
-
Static synchronous design
-
Positive edge clocking and no internal tri-states
-
Scan test ready
-
Simple interface allows easy connection to microprocessor/microcontroller devices
Benefits
-
Single Site license option is provided to companies designing in a single site.
-
Multi Sites license option is provided to companies designing in multiple sites.
-
Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
-
Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
Deliverables
-
The SAE J1850 interface is available in Source and netlist products.
-
The Source product is delivered in Verilog. If needed VHDL, SystemC code can also be provided.
-
Easy to use Verilog Test Environment with Verilog Testcases.
-
Lint, CDC, Synthesis, Simulation Scripts with waiver files.
-
IP-XACT RDL generated address map.
-
Firmware code and Linux driver package.
-
Documentation contains User's Guide and Release notes.
