Description
The FlexRay Controller IP Core is full-featured, easy-to- use, synthesizable design that is easily integrated into any SoC or FPGA development. The FlexRay Controller IP can be implemented in any technology. The FlexRay Controller IP core is compliant with the FlexRay 3.0.1 Specification. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses. The FlexRay Controller IP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The FlexRay Controller IP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.
Features
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Compliant with FlexRay 3.0.1 Specification.
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Support Full Duplex of operations.
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Complete Flexray Transmitter/ Receiver functionality.
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Supports cluster wakeup and startup.
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Transmit and receive commands allow the user to transmit and receive Flexray data.
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Supports 2.5, 5 and 10 Mbit/s bitrate.
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Support Bit alignment
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All types of frame generation. • Static frames • Dynamic frames
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Various kinds of Tx and Rx errors detection.
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Syntax errors • Frame ID error (Frame ID = 0) • Header CRC error • CRC error • Over and undersize errors
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Content errors • Cycle Count error • Frame ID error • Startup, Sync & Null frame errors w.r.t Dynamic • Startup & Sync frame errors w.r.t Static segment • Reception of Null frame
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Fully synthesizable.
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Static synchronous design.
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Positive edge clocking and no internal tri-states.
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Scan test ready.
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Simple interface allows easy connection to microprocessor/microcontroller devices.
Deliverables
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RTL design in Verilog
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Lint, CDC, Synthesis Scripts with waiver files
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Lint, CDC, Synthesis Reports
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IP-XACT RDL generated address map
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Firmware code and Linux driver package
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Technical documentation in greater detail
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Easy to use Verilog Test Environment with Verilog Testcases
