LIN FlexD Controller IP

Description

The Local Interconnect Network's (LIN) soft core is the LIN. This interface uses a serial communication protocol that was primarily created for usage in automotive applications. The LIN is slower than the CAN but considerably more affordable because of how straightforward it is. When the bandwidth and adaptability of the CAN are not needed, our Core is the best option for communication in intelligent sensors and actuators. A microprocessor or microcontroller and the LIN bus are connected via the LIN core. Depending on the work mode selected by the CPU or microcontroller, it can function as a master or slave LIN node. This controller can transmit and receive LIN messages compatible with LIN 1.3, LIN 2.1, and other LIN versions since it supports transmission speeds between 1 and 20 kb/s.

Features

• Conforms with LIN 1.3, LIN 2.1 and LIN 2.2 specification.
• Automatic LIN Header handling
• Automatic Re-synchronization
• Data rate between 1Kbit/s and 20 Kbit/s
• Master and Slave work mode
• Time-out detection
• Extended error detection
• “Break-in-data” support
• Available system interface wrappers:
• AMBA – APB Bus
• Altera Avalon Bus
• Xilinx OPB Bus

Deliverables

• Source code:
• VHDL Source Code or/and
• VERILOG Source Code or/and
• Encrypted, or plain text EDIF
• VHDL & VERILOG test bench environment
• Active-HDL automatic simulation macros
• ModelSim automatic simulation macros
• Tests with reference responses
• Technical documentation
• Installation notes
• HDL core specification
• Datasheet
• Synthesis scripts
• Example application
• Technical support

Applications

• Automotive
• Industrial
• Embedded communication systems