› USB › USB 4.0 Host Controller IP
TSMC 40LP /LL
UMC 28HPC+/ HPC
UMC 55SP /EF
SMIC 14SF+/ SF++
USB 4.0 Host Controller IP
Description and Features
The USB 4.0 Host controller IP is a highly configurable core and implements the USB 4.0 Host functionality that can be interfaced with third party USB 4.0 PHY's. The USB 4.0 Device IP core is latest development that enables designers in the PC, mobile, consumer and communication markets to bring significant power and performance enhancements to the popular USB standard while offering backwards compatibility with billions of USB-enabled devices currently in the market. It is validated using FPGA prototype with industry standard PHYs.
Initial Versions :
A single downstream USBv4 Port
PCIe Host Interface Adaptor
No DP Source or PCIe Controller
Subsequent Versions :
Include xHCI Controller
No DP or PCIe Controller
Configurable Number of Downstream USBv4 Ports
Optional support for DP Source Adaptor
Optional support for PCIe Down Adaptor
PCIe based host interface adaptor with support for RAW and Frame mode.
Configurable option to exclude xHCI Controller and USB3 Down adaptor.
Optionally a reference firmware running on micorblaze for emulating connection manager for very simple topology.
Supports USB4 Gen 2x2 (20 Gbps) and USB4 Gen 3x2 (40 Gbps) Links.
Optional support for thunderbolt Gen 2 (10.3125 Gbps) & Gen 3 (20.625 Gbps) rates.
Optional bypass mode to support native USB v3.2
Support for Alt Mode and Billboard class via USB2 controller.
USB 4.0 increases data rates up to a minimum of 20Gbps (40Gbps is also supported)
USB 4.0 Device is virtually identical in protocol and thus retaining backwards compatibility with older versions 3.2,3.0, 2.0
Supports PIPE and UTMI+ PHY interfaces
Architectural features reduce power consumption
Optimized Host controller IP designed to achieve power boost
Mass storage devices
Display and docking applications
Configurable RTL Code
HDL based test bench and behavioral models
Protocol checkers, bus watchers and performance monitors
Configurable synthesis shell
FPGA Platform for Pre-Tape-out Validation