USB3 Vision and Video Class Device controller are designed for compliance with USB Vision Specification, USB Video Class Specification, USB3.1 specification, Revision 1.0 and all associated ECN’s, USB specifications Rev 2.0 and all associated ECN’s. USB3 Vision and Video Class Device Controller optionally include support for USB Audio Class support to provide full functionality for implementing USB Cameras.
USB3 Vision and Video Class Device controller can optionally include a proprietary EP0 processor block for managing all Standard Requests directed to the control endpoint minimizing software development overhead. Class and Vendor specific requests directed to Control endpoint are routed via a simple slave register access interface to software for processing. USB Vision and Video Class Device Controller provides a simple streaming interface to allow user logic to forward the image data to the IP. USB controller handles all USB specific packetizing for USB Vision and Video Class applications. USB Vision and Video Class Device provides a simple mechanism to forward all necessary information for packetizing on a frame by frame basis. We also provide reference firmware which can be reused by customer to build the relevant device side firmware for managing the camera control transfers based on GenCP Specification. Additionally we also provide a very simple test image generator which can generate test images to help in isolating USB specific issues and debugging the complete path from the camera sensor to the application running on the USB host.
Boasts a design that's highly adaptable and can be configured to suit various needs and setups.
Utilizes a structured layered architecture, aiding in organized development and seamless scalability.
Operates with precision and efficiency thanks to its fully synchronous design.
Offers flexibility in system control with support for both synchronous and asynchronous resets.
Ensures clarity and efficiency in system timing with distinct clock domains.
Maximizes energy efficiency through extensive clock gating support.
Facilitates sophisticated power management strategies with support for multiple power wells.
Empowers users with software-driven control over critical features, enhancing customization and ease of use.
Tailored RTL Code Configuration
HDL-Based Test Bench with Behavioral Models
Test Cases Suite
Protocol Validators, Bus Observers, and Performance Monitors
Customizable Synthesis Framework
Design Documentation
Verification Guidelines
Synthesis Manual
FPGA Validation Platform for Pre-Tape-out Testing
Firmware Implementation Reference
