Description and Features
The IEC7816 Slave Controller IP Core is full-featured, easy-to-use, synthesizable designs that are easily integrated into any SoC or FPGA development. The IEC7816 Slave controller IP can be implemented in any technology. The Slave controller IP core supports the ISO/IEC 7816-3 standard. It can also support a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses. The Slave IP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The Slave IP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.
Features
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Compliant with ISO/IEC 7816-3 Specification.
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Full IEC7816-3 Slave functionality.
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Supports all functions for complete smart card sessions, including • Card activation and deactivation • Cold/warm reset • Answer to Reset (ATR) response reception • Data transfers to and from the card
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Supports adjustable clock rate and bit (baud) rate.
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Supports configurable automatic byte repetition.
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Supports commonly used communication protocols • T = 0 for asynchronous half-duplex character transmission, and • T = 1 for asynchronous half-duplex block transmission
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Fully synthesizable
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Static synchronous design
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Positive edge clocking and no internal tri-states
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Scan test ready
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Simple interface allows easy connection to microprocessor/microcontroller devices
Deliverables
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RTL design in Verilog
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Lint, CDC, Synthesis Script with waiver files
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Lint, CDC, Synthesis Reports
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IP-XACT RDL generated address map
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Firmware code and Linux driver package
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Technical documentation in greater detail
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Easy to use Verilog Test Environment with Verilog Test cases
