Description and Features

An ultra-low-power programmable fractional-N (ULF), phase-locked loop (PLL) at 1.4GHz for frequency synthesis available at 40nm.

Features

• Designed to be power-efficient
• Fractional Division
• High Resolution of 1.4GHz
• Low Jitter
• control the phase and frequency characteristics
• Programmable Loop Filter
• Lock Detection
• Small Footprint        

Deliverables

• GDSII
• LVS Spice netlist
• Verilog model
• LEF for clock generator
• PLL
• User Guidelines including:
•   integration guidelines
•   layout guidelines
•   testability guidelines
•   packaging guidelines
•   board-level guidelines