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T2M › Verification IPs › MIPI C-PHY VIP

MIPI C-PHY VIP

Description

The MIPI CPHY Verification IP validates CPHY devices and complies with the MIPI CPHY specification. Experts with experience in developing complicated protocols have created the CPHY Verification IP. SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E, and non-standard verification environments all natively support the MIPI CPHY Verification IP. In order to speed up debugging, the MIPI CPHY Verification IP offers an optional Smart Visual Protocol Debugger that is GUI based.

MIPI-C-PHY-VIP-silicon-proven-ip-supplier-in-taiwan

Features
  • Full MIPI CPHY Transmitter and Receiver functionality.
  • Supports 2.0 MIPI CPHY Specifications.
  • Supports up to 32 trio lanes.
  • Supports both serial and PPI functionality testing.
  • Supports PRBS Pattern generation.
  • Supports short and long packets
  • Supports BTA Operations.
  • Supports to set symbol clock
  • Supports to set lane skew between lanes in a trio for arrival of sot.
  • Supports all lane configuration
  • Supports multiple packets per transmission
  • Supports different SYNC word in serial and PPI.
  • Supports Calibration preamble formats in serial.
  • Supports ALP mode in serial and PPI.
  • Supports differential and single ended mode of operation
  • Various kind of Transmitter and Receiver errors generation and detection • SoT Error • SoT Sync Error • EoT Sync Error • Escape Entry Command Error • False Control Error
  • Status counters for various events in bus.
  • Operates as a Transmitter, Receiver
  • Monitor, Detects and notifies the test bench of all protocol and timing errors.
  • Callbacks in node transmitter, receiver and monitor for user processing of data.
  • MIPI CPHY Verification IP comes with complete test suite to test every feature of MIPI CPHY specification.
  • Functional coverage for complete MIPI CPHY features

Deliverables

  • Complete regression suite containing all the MIPI CPHY testcases.
  • Examples showing how to connect various components, and usage of Tx,Rx and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes
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