MIPI CPHY Verification IP is compliant with MIPI CPHY specification and verifies CPHY devices. CPHY Verification IP is developed by experts who have worked on complex protocols before. MIPI CPHY Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env. MIPI CPHY Verification IP comes with optional Smart Visual Protocol Debugger, which is GUI based debugger to speed up debugging.
Full MIPI CPHY Transmitter and Receiver functionality.
Supports 2.0 MIPI CPHY Specifications.
Supports up to 32 trio lanes.
Supports both serial and PPI functionality testing.
Supports PRBS Pattern generation.
Supports short and long packets
Supports BTA Operations.
Supports to set symbol clock
Supports to set lane skew between lanes in a trio for arrival of sot.
Supports all lane configuration
Supports multiple packets per transmission
Supports different SYNC word in serial and PPI.
Supports Calibration preamble formats in serial.
Supports ALP mode in serial and PPI.
Supports differential and single ended mode of operation
Various kind of Transmitter and Receiver errors generation and detection • SoT Error • SoT Sync Error • EoT Sync Error • Escape Entry Command Error • False Control Error
Status counters for various events in bus.
Operates as a Transmitter, Receiver
Monitor, Detects and notifies the test bench of all protocol and timing errors.
Callbacks in node transmitter, receiver and monitor for user processing of data.
MIPI CPHY Verification IP comes with complete test suite to test every feature of MIPI CPHY specification.
Functional coverage for complete MIPI CPHY features
Complete regression suite containing all the MIPI CPHY testcases.
Examples showing how to connect various components, and usage of Tx,Rx and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes