Production Proven, Complex Semiconductor IP Cores

IP Cores


T2M DisplayPort V-by-One/LVDS Tx Combo PHY in 28HPC+

V-by-One/LVDS Tx Combo PHY in 28HPC+

Description and Features

V-by-One/ LVDS Tx Combo PHY IP Core aims at achieving high-speed data transmission for video signals through internal equipment connections. The V-by-One® HS Standard establishes specifications for developing both transmitters and receivers. It supports speeds of up to 4Gbps per lane, with options for 8-lane and 16-lane PHY configurations for both transmission and reception. Additionally, V-by-One/ LVDS Tx Combo PHY IP for transmitter is available, comprising 20-lane (4 x 4D1C) LVDS drivers, supporting data rates of up to 1.5Gbps. These capabilities facilitate efficient and reliable data transmission, meeting the demands of modern digital video systems with enhanced performance and versatility.

Features
  • LVDS compliant Tx

  • 4 groups of 4-Data

  • 1-Clock channels Each lane/group can be turned on/off individually Data/Clock can be assigned to any lane within the group

  • Differential polarity can be flip per lane

  • Supports from 168Mbps to 1.5Gbps data rate

  • Supports reduced swing mode

  • X7 Multiplier PLL for serial clock generation

  • Configurable analog characteristics

  • PLL loop filter

  • PLL VCO gain

  • Differential voltage Common-mode voltage

  • Pre-emphasis strength

  • Silicon Proven in TSMC 28HPC+

Deliverables

  • Datasheet

  • Integration guideline

  • GDSII or Phantom

  • GDSII Layer map table

  • CDL netlist for LVS

  • LEF Verilog behavior model

  • Liberty timing model DRC/LVS/ERC results