DDR3L interface provides full support for the DDR3L interface, compatible with DDR3L protocol standard of 8GB_DDR3L and DFI-version 3.1 or higher Specification Compliant. Through its DDR3L compatibility, it provides a simple interface to a wide range of low-cost devices. DDR3L IP is proven in FPGA environment. The host interface of the DDR3L can be simple interface or can be AMBA AHB, AMBA AHB-Lite, AMBA APB, AMBA AXI, AMBA AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or Custom protocol.
DDR3L interface provides full support for the DDR3L
Supports DDR3L protocol standard of interface, compatible with DDR3L protocol standard
of 8GB_DDR3L and DFI-version 3.1 or higher
Compliant with DFI-version 3.1 or higher
Specification Compliant. Through its DDR3LSpecification.
compatibility, it provides a simple interface to a wide range of low-cost devices. DDR3L IP is proven
Supports up to 8 GB device density.
Supports Programmable Write latency and Read in FPGA environment.
The host interface of the latency.
DDR3L can be simple interface or can be AMBA AHB, AMBA AHB-Lite, AMBA APB, AMBA AXI, AMBA
Supports On-the-fly for burst length.
Supports Programmable burst lengths: 4, 8.AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone
Supports for All Mode register programming. or Custom protocol.
Supports 8 internal banks.
Supports the following devices o X4 o X8 o X16
Supports the following burst order
Supports for Write data Mask.
Supports for Power Down features.
Supports for input clock stop and frequency change.
Supports for DLL.
Supports for Write leveling.
Supports for automatic self refresh(ASR). Supports for self refresh mode.
Supports for Self Refresh Temperature (SRT). Supports for Multipurpose Register.
Supports for Nominal and dynamic ODT (On-Die Termination) for data, strobe and mask signals.
Supports up to 16 AXI ports with data width up to 512 bits.
Supports controllable outstanding transactions for AXI write and read channels
Supports in port arbitration and multi-port arbitration.
Supports Error Checking and correction (ECC).
Supports retry on ECC error, with retry limit user controllable.
Supports high clock speeds in ASIC and FPGA. Supports user programmable page policy.
Closed page policy
Open page policy
Supports all speed grades as per specification. Supports reordering of transactions for higher performance.
Quickly validates the implementation of the DDR3L standard of 8GB_DDR3L
Deliverables
The DDR3L interface is available in Source and netlist products.
The Source product is delivered in Verilog. If needed VHDL, SystemC code can also be provided.
Easy to use Verilog Test Environment with Verilog Testcases Lint, CDC, Synthesis, Simulation Scripts with waiver files IP-XACT RDL generated address map
Firmware code and Linux driver package Documentation contains User's Guide and Release notes.
