Description and Features
DDR3L interface provides full support for the DDR3L interface, compatible with DDR3L protocol standard of 8GB_DDR3L and DFI-version 3.1 or higher Specification Compliant. Through its DDR3L compatibility, it provides a simple interface to a wide range of low-cost devices. DDR3L IP is proven in FPGA environment. The host interface of the DDR3L can be simple interface or can be AMBA AHB, AMBA AHB-Lite, AMBA APB, AMBA AXI, AMBA AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or Custom protocol.

Features
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Supports DDR3L protocol standard of 8GB_DDR3L.pdf.
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Compliant with DFI-version 3.1 or higher Specification.
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Supports up to 8 GB device density.
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Supports Programmable Write latency and Read latency.
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Supports On-the-fly for burst length.
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Supports Programmable burst lengths: 4, 8.
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Supports for All Mode register programming.
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Supports 8 internal banks.
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Supports the following devices • X4 • X8 • X16
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Supports the following burst order • Sequential • Interleave
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Supports for Write data Mask.
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Supports for Power Down features.
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Supports for input clock stop and frequency change.
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Supports for DLL.
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Supports for Write leveling.
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Supports for automatic self refresh(ASR).
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Supports for self refresh mode.
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Supports for Self Refresh Temperature (SRT).
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Supports for Multipurpose Register.
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Supports for Nominal and dynamic ODT (On-Die Termination) for data, strobe and mask signals.
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Supports up to 16 AXI ports with data width up to 512 bits.
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Supports controllable outstanding transactions for AXI write and read channels
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Supports in port arbitration and multi-port arbitration.
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Supports Error Checking and correction (ECC).
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Supports retry on ECC error, with retry limit user controllable.
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Supports high clock speeds in ASIC and FPGA.
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Supports user programmable page policy. • Closed page policy • Open page policy
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Supports all speed grades as per specification.
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Supports reordering of transactions for higher performance.
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Quickly validates the implementation of the DDR3L standard of 8GB_DDR3L.pdf.
Deliverables
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The DDR3L interface is available in Source and netlist products.
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The Source product is delivered in Verilog. If needed VHDL, SystemC code can also be provided.
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Easy to use Verilog Test Environment with Verilog Testcases
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Lint, CDC, Synthesis, Simulation Scripts with waiver files
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IP-XACT RDL generated address map
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Firmware code and Linux driver package
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Documentation contains User's Guide and Release notes.